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d1912hkpc 20121129-s00003/71112hk no.a2089-1/11 http://onsemi.com semiconductor components industries, llc, 2013 august, 2013 ver1.0.1 LC717A00AJ overview the LC717A00AJ is a high-performance, low-cost capacitan ce-digital-converter lsi for electrostatic capacitive touch sensor, especially focused on usability. it has 8 channels cap acitance-sensor input. the built-in logic circuit can detect the state (on/off) of each input and output the result. this makes it id eal for various switch applications. the calibration function is automatically performed by the built-in logic circuit during power activation or whenever there are environmental changes. in addition, since initia l settings of parameters, such as gain, are configured, LC717A00AJ can operate as stan d-alone when the recommended switch pattern is applied. also, since LC717A00AJ has a serial interface compatible with i 2 c and spi bus, parameters can be adjusted using external devices whenever necessary. moreover, outputs of th e 8-input capacitance data can be detected and measured as 8-bit data. features ? detection system: differential capacitance detection (mutual capacitance type) ? input capacitance resolution: can detect capacitance changes in the femto farad order ? measurement interval (8 differential inpu ts): 18ms (typ) (at initial configuration), 3ms (typ) (at minimum interval configuration) ? external components for measurement: not required ? current consumption: 320 a (typ) (v dd = 2.8v), 740 a (typ) (v dd = 5.5v) ? supply voltage: 2.6v to 5.5v ? detection operations: switch ? packages: ssop30 ? interface: i 2 c * compatible bus or spi selectable. ordering number : ena2089a cmos lsi capacitance-digital-converter lsi for electrostatic capacitive touch sensors * i 2 c bus is a trademark of philips corporation.
LC717A00AJ no.a2089-2/11 specifications absolute maximum ratings at ta = +25 c parameter symbol ratings (v ss = 0v) unit remarks supply voltage v dd -0.3 to +6.5 v input voltage v in -0.3 to v dd +0.3 v *1 output voltage v out -0.3 to v dd +0.3 v *2 power dissipation pd max 160 mw ta = +105 c, mounted on a substrate *3 peak output current i op 8 ma per terminal, 50% duty ratio *2 total output current i oa 40 ma output total value of lsi, 25% duty ratio storage temperature tstg -55 to +125 c *1) apply to cin0 to 7, cref, nrst, scl, sda, sa, sck, si, ncs, gain *2) apply to cdrv, pout0 to 7, sda, so, error, intout *3) single-layer glass epoxy board (76.1 114.3 1.6t mm) recommended operating conditions parameter symbol conditions min typ max unit remarks operating supply voltage v dd 2.6 5.5 v supply ripple + noise vpp 20 mv *1 operating temperature topr -40 25 105 c *1) inserting a high-valued capacitor and a low-valued capacitor in parallel between v dd and v ss is recommended. in this case, the small-valued capacitor should be at least 0.1 f, and is mounted near the lsi. electrical characteristics at v ss = 0v, v dd = 2.6 to 5.5v, ta = -40 to +105 c * unless otherwise specified, the cdrv drive frequency is f cdrv = 143khz. * not tested at low temperature before shipment. parameter symbol conditions min typ max unit remarks capacitance detection resolution n 8 bit output noise rms n rms minimum gain setting 1.0 lsb *1 *3 input offset capacitance adjustment range coff range 8.0 pf *1 *3 input offset capacitance adjustment resolution coff reso 8 bit cin offset drift cin drift minimum gain setting 8 lsb *1 cin detection sensitivity cin sense minimum gain setting 0.04 0.12 lsb/ff *2 cin pin leak current i cin cin = hi-z 25 500 na cin allowable parasitic input capacitance cin sub cin against v ss 30 pf *1 *3 cdrv drive frequency f cdrv 100 143 186 khz cdrv pin leak current i cdrv cdrv = hi-z 25 500 na nrst minimum pulse width t nrst 1 s *1 power-on reset time t por 20 ms *1 power-on reset operation condition: hold time t porop 10 ms *1 power-on reset operation condition: input voltage v porop 0.1 v *1 power-on reset operation condition: power supply rise rate t vdd 0v to v dd 1 v/ms *1 v ih high input 0.8v dd pin input voltage v il low input 0.2v dd v *1 *4 v oh high output (i oh = +3ma) 0.8v dd pin output voltage v ol low output (i ol = -3ma) 0.2v dd v *5 continued to the next page. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LC717A00AJ no.a2089-3/11 continued from the previous page. parameter symbol conditions min typ max unit remarks sda pin leak current v ol i 2 c sda low output (i ol = -3ma) 0.4 v pin leak current i leak 1 a *6 when stand-alone configuration and non-touch v dd = 2.8v 320 390 i dd when stand-alone configuration and non-touch v dd = 5.5v 740 900 a *1 *3 current consumption i stby during sleep process 1 a *3 *1) design-guaranteed values (not tested before shipment) *2) measurements conducted using the test mode in the lsi *3) ta = +25 c *4) apply to nrst, scl, sda, sa, sck, si, ncs, gain *5) apply to cdrv, pout0 to 7, so, error, intout *6) apply to nrst, scl, sda, sa, sck, si, ncs, gain
LC717A00AJ no.a2089-4/11 i 2 c compatible bus timing characteristics at v ss = 0, v dd = 2.6 to 5.5v, ta = -40 to +105 c *not tested at low temp erature before shipment parameter symbol pin name conditions min typ max unit remarks scl clock frequency f scl scl 400 khz start condition hold time t hd;sta scl sda 0.6 s scl clock low period t low scl 1.3 s scl clock high period t high scl 0.6 s repeated start condition setup time t su;sta scl sda 0.6 s *1 data hold time t hd;dat scl sda 00.9 s data setup time t su;dat scl sda 100 s *1 sda, scl rise/fall time t r / t f scl sda 300 s *1 stop condition setup time t su;sto scl sda 0.6 s stop-to-start bus release time t buf scl sda 1.3 s *1 * 1) design-guaranteed values (not tested before shipment) spi bus timing characteristics at v ss = 0, v dd = 2.6 to 5.5v, ta = -40 to +105 c *not tested at low temp erature before shipment parameter symbol pin name conditions min typ max unit remarks sck clock frequency f sck sck 5 mhz sck clock low time t low sck 90 ns *1 sck clock high time t high sck 90 ns *1 input signal rise/fall time t r / t f ncs sck si 300 ns *1 ncs setup time t su;ncs ncs sck 90 ns *1 sck clock setup time t su;sck ncs sck 90 ns *1 data setup time t su;si sck si 20 ns *1 data hold time t hd;si sck si 30 ns *1 ncs hold time t hd;ncs ncs sck 90 ns *1 sck clock hold time t hd;sck ncs sck 90 ns *1 ncs standby pulse width t cph ncs 90 ns *1 output high impedance time from ncs t chz ncs so 80 ns *1 output data determination time t v sck so 80 ns *1 output data hold time t hd;so sck so 0 ns *1 output low impedance time from sck clock t clz sck so 0 ns *1 * 1) design-guaranteed values (not tested before shipment)
LC717A00AJ no.a2089-5/11 power-on reset (por) when power is turned on, power-on reset is enabled inside th e lsi and its state is released after a certain power-on reset time, t por. power-on reset operation condition: power supply rise rate t vdd must be at least 1v/ms. since intout pin changes from ?high? to ?low? at the same time as the released of power-on reset state, it is possible to verify the t por externally. during power-on reset state, cin, cref and pout are unknown. fig.1 i 2 c compatible bus data timing fig.2 i 2 c compatible bus communication formats ? write format (data can be written into sequentially incremented addresses) start slave address write=l register address (n) ack ack data written to register address (n) ack data written to register address (n+1) ack stop slave slave slave slave fig.3 ? read format (data can be read from sequentially incremented addresses) start slave address write=l register address (n) ack ack data read from register address (n) ack restart slave address read=h ack data read from register address (n+1) ack data read from register address (n+2) nack stop slave slave slave master master master fig.4 sda scl start condition t hd;sta t low t hi g h t r repeated start condition stop condition 10% t f 90% 10% 10% 90% 90% t hd;dta t su;dta 10% 10% 10% 90% t su;sta 90% 90% t hd;sta 90% 10% 90% 10% 90% 10% t su;sto t buf start condition 90% por (lsi internal signal) release t p o r v dd reset t vdd intout v p o r o p cin, cref, pout unknown valid t p o r o p unknown unknown unknown reset release t p o r valid
LC717A00AJ no.a2089-6/11 i 2 c compatible bus slave address selection of two kinds of addresses is possible through the sa terminal. sa pin input 7bit slave address binary notation 8bit slave address 00101100b (write) 0x2c low 0x16 00101101b (read) 0x2d 00101110b (write) 0x2e high 0x17 00101111b (read) 0x2f spi data timing (spi mode 0 / mode 3) fig.5 spi communication formats (example of mode 0) ? write format (data can be written into sequentia lly incremented addresses while holding ncs = l) ncs sck si so 76543 2 10 hi-z register address(n) data written to register address(n) data written to register address(n+1) write=l 76543 2 10 76543 2 10 fig.6 ? read format (data can be read from sequentially incremented addresses while holding ncs = l) register address(n) data read from register address(n) data read from register address(n+1) 7 read=h 76543 2 10 hi-z ncs sck si so 76543 2 10 76543 2 10 fig.7 ncs sck si so t su;si valid hi-z t r t hd;si t su;sck t su;ncs t high t low t f t cph t hd;ncs t hd;sck t clz t hd;so t chz valid t v
LC717A00AJ no.a2089-7/11 package dimensions [LC717A00AJ] unit : mm (typ) 3421 pin assignment pin no. pin name pin no. pin name 1 v dd 16 cref 2 v ss 17 error 3 non connect *1 18 cdrv 4 cin4 19 intout 5 cin5 20 gain 6 cin6 21 scl/sck 7 cin7 22 sda/si 8 pout0 23 sa/so 9 pout1 24 ncs 10 pout2 25 nrst 11 pout3 26 non connect *1 12 pout4 27 cin0 13 pout5 28 cin1 14 pout6 29 cin2 15 pout7 30 cin3 *1) connect to gnd when mounted sanyo : ssop30(225mil) 8.0 4.4 0.1 6.4 12 30 0.15 0.5 0.22 0.5 (0.5) 1.7 max (1.5)
LC717A00AJ no.a2089-8/11 block diagram cin0 scl/sck sda/si v dd v ss intout cin1 cin2 cin3 cin4 cin5 cin6 cin7 pout0 pout1 pout6 pout7 pout5 pout4 pout3 pout2 ncs sa/so cdrv gain nrst error cref mux 1st amp a/d converter 2nd amp por control logic oscillator i 2 c/spi LC717A00AJ is capacitance-digital-converter lsi capable of de tecting changes in capacitance in the femto farad order. it consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system when the power is turned on, a multiplexer that selects the input ch annels, a two-stage amplifier th at detects the changes in the capacitance and outputs analog-amplitude values, a a/d converter that converts the analog-amplitude values into digital data, and a control logic that controls the entire chip. also, it has an i 2 c compatible bus or spi that enables serial communication with external devices as necessary.
LC717A00AJ no.a2089-9/11 pin functions pin name i/o pin functions pin type cin0 i/o capacitance sensor input cin1 i/o capacitance sensor input cin2 i/o capacitance sensor input cin3 i/o capacitance sensor input cin4 i/o capacitance sensor input cin5 i/o capacitance sensor input cin6 i/o capacitance sensor input cin7 i/o capacitance sensor input cref i/o reference capacitance input r amp v dd v ss buffer pout0 o cin0 judgment result output pout1 o cin1 judgment result output pout2 o cin2 judgment result output pout3 o cin3 judgment result output pout4 o cin4 judgment result output pout5 o cin5 judgment result output pout6 o cin6 judgment result output pout7 o cin7 judgment result output error o error occurrence status output cdrv o output for capacitance sensors drive intout o interrupt output v dd v ss buffer scl/sck i clock input (i 2 c) / clock input (spi) gain i selection pin of the initial value of gain of the 2nd-amplifier ncs i interface selection / chip select inverting input (spi) nrst i external reset signal inverting input v dd v ss r sda/si i/o data input and output (i 2 c) / data input (spi) v dd v ss r sa/so i/o slave address selection (i 2 c) / data output (spi) v dd v ss r buffer v dd power supply (2.6v to 5.5v) *1 v ss ground (earth) *1 *2 * 1) inserting a high-valued capacitor and a low-valued capacitor in parallel between v dd and v ss is recommended. in this case, the small-valued capacitor should be at least 0.1 f, and is mounted near the lsi. * 2) when v ss terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.
LC717A00AJ no.a2089-10/11 details of pin functions cin0 to cin7 these are the capacitance-sensor-input pins. these pins are used by connecting them to the touch switch pattern. cin and the cdrv wire patterns shou ld be close to each other. by doing so, cd rv and cin patterns are capacitively coupled. therefore, lsi can detect capacitance cha nge near each pattern as 8bit digital data. however, if the shape of each pattern or the capacitively coupl ed value of cdrv is not appropriate, it may not be able to detect the capacitance change correctly. in this lsi, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. cin0 to cin7 are connected to the inverting input of the 1 st amplifier. during measurement process, channels other than the one being measured are all in ?low? condition. leave the unused terminals open. cref it is the reference-capacitance-input pin. it is used by connecting to the wire pattern like cin pins or is used by connecting any capacitance between this pin and cdrv pin. in this lsi, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. cref is connected to the non-inverting input of the 1 st amplifier. due to the parasitic capacitance generated in the wire connec tions of cin pins and their patterns, as well as the one generated between the wire patterns of cin and cdrv pins, cref may not detect capacitance change of each cin pin accurately. in this case, connect an appropriate capacitan ce between cref and cdrv to detect capacitance change accurately. however, if the difference between the parasitic capacitan ce of each cin pin is extremely large, it may not detect capacitance change in each cin pin correctly. pout0 to pout7 these are the detection-result-output pins. the capacitance det ection results of cin0 to cin7 are compared with the threshold of the lsi. the pin outputs a ?high? or a ?low? depending on the result. error it is the error-occurrence-status-output pin. it outputs ?low? during normal operation. if there is a calibration error or a syst em error, it outputs ?high? to indicate that an error occurred. cdrv it is the output pin for capacitance sensors drive. it output s the pulse voltage which is needed to detect capacitance at cin0 to cin7. cdrv and cin wire patterns should be close to each other so that they are capacitively coupled. intout it is the interrupt-output pin. it outputs ?high? when a measurement process is completed. connect to a main microcomputer if necessary, and use as interrupt signal. leave the terminal open if not in used. scl/sck clock input (i 2 c) / clock input (spi) it is the clock input pin of the i 2 c compatible bus or the spi depending on the mode of operation. if interface is not to be used, fix the pin to ?high?. ho wever, even if interface is not to be used, providing a communication terminal on board is still recommended. gain in this lsi, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. it is the selection pin of the initial value of gain of the 2 nd amplifier. even if this lsi is used alone, gain setting can still be sel ected through this terminal. at initialization of the lsi, it is set to 7-times higher than the minimum setting when gain pin is ?low?, and is set to 14-times higher than the minimum setting when gain pin is ?high?.
LC717A00AJ no.a2089-11/11 ncs interface selection / chip-select-inverting input (spi) selection of i 2 c compatible bus mode or spi mode is through this terminal. after initialization, the lsi is automatically in i 2 c compatible bus mode. to continually use i 2 c compatible bus mode, fix ncs pin to ?high?. to switch to spi mode after lsi initialization, change the ncs input ?high? ?low?. the ncs pin is used as the chip- select-inverting input pin of spi, and spi m ode is kept until lsi is again initialized. if interface is not to be used, fix the pin to ?high?. nrst it is the external-reset-signal-inverting-input pin. wh en nrst pin is ?low?, lsi is in the reset state. each pin (cin0 to 7, cref, pout,0 to 7, error) is ?hi-z? during reset state. sda/si data input and output (i 2 c) / data input (spi) it is the data input and output pin of the i 2 c compatible bus or the data input pin of the spi depending on the mode of operation. if interface is not to be used, fix the pin to ?high?. ho wever, even if interface is not to be used, providing a communication terminal on board is still recommended. sa/so slave address selection (i 2 c) / data output (spi) it is the slave address selection pin of the i 2 c compatible bus or the data output pin of the spi depending on the mode of operation. if interface is not to be used, fix the pin to ?high?. ho wever, even if interface is not to be used, providing a communication terminal on board is still recommended. ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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